1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines the performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
In contrast to a FET, which has a planar structure, there are so-called 3D devices (3-dimensional structures), such as an illustrative FinFET device. More specifically, in one illustrative embodiment of a FinFET, a generally vertically positioned fin-shaped active area is formed, and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure with a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device may only have a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced relative to that of a planar FET device, which tends to reduce at least some short channel effects on a FinFET device.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. The gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and further scaling or reduction of the gate length is anticipated in the future. Device designers have employed a variety of techniques, other than device scaling, in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors), etc.
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by performance increases associated with the scaling of device features. Generally, while decreasing the channel length of a transistor may lead to superior performance characteristics, such as higher drive current capabilities and enhanced switching speeds, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
The use of so-called high-k/metal gate structures in replacement gate process flows to increase device electrical performance, while generally successful, has created some issues that need to be addressed. For example, after the deposition of a high-k insulating material, a post-deposition anneal is performed at a temperature that is typically greater than approximately 750° C. to insure adequate reliability of the gate stack materials. Metal silicide regions are typically formed on a transistor where contact is to be made to an underlying device, e.g., to the source/drain regions and/or the gate electrode, to reduce the contact resistance and hopefully improve the operating speed of the transistor. To the extent that metal silicide regions are formed prior to this post-deposition anneal process that is performed in a replacement gate process flow, the anneal process tends to cause the metal silicide regions to degrade, thereby increasing contact resistance and perhaps reducing the operating speed of the transistor.
The present disclosure is directed to various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices that may eliminate or at least reduce one or more of the problems identified above.